Deep trench isolation shrinkage method for enhanced device performance

ABSTRACT

Some embodiments of the present disclosure relate to a deep trench isolation (DTI) structure configured to enhance efficiency and performance of a photovoltaic device. The photovoltaic device comprises a functional layer disposed over an upper surface of a semiconductor substrate, and a pair of pixels formed within the semiconductor substrate, which are separated by the DTI structure. The DTI structure is arranged within a deep trench. Sidewalls of the deep trench are partially covered with a protective sleeve formed along the functional layer prior to etching the deep trench. The protective sleeve prevents etching of the functional layer while etching the deep trench, which prevents contaminants from penetrating the pair of pixels. The protective sleeve also narrows the width of the DTI structure, which increases pixel area and subsequently the efficiency and performance of the photovoltaic device.

BACKGROUND

The present disclosure relates to deep trench isolation techniques, suchas used in photovoltaic devices.

Photovoltaic devices are used in a wide variety of electronicsapplications ranging from image sensors, to optical detectors, totelecommunications, etc. Many photovoltaic devices utilize an array ofpixels, which include photodiodes that convert an image into digitaldata. A photodiode consists of a p-n junction arranged between an anodeand a cathode. When incident radiation from an image is absorbed near adepletion region of the p-n junction, an electron-hole pair is created.The electron is drawn to cathode and the hole is drawn to the anode toproduce a photocurrent.

Some photodiodes are formed directly on a semiconductor substratealongside an integrated circuit during a semiconductor manufacturingprocess. These photodiodes provide an advantage of lower powerconsumption, smaller size, faster data processing, and lowermanufacturing cost than photodiodes formed external to the semiconductorsubstrate. The properties of a photodiode formed on a semiconductorsubstrate are determined from the bandgap of the semiconductorsubstrate, because the bandgap determines what wavelengths of incidentlight will excite electron-hole pairs to produce the photocurrent.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a perspective view of a deep trench isolation (DTI)structure in accordance with some embodiments.

FIGS. 2A-2C illustrate cross-sectional views of photovoltaic devices inaccordance with some embodiments.

FIGS. 3A-3F illustrate a series of cross-sectional views thatcollectively depict forming a DTI structure in accordance with someembodiments.

FIG. 4 illustrates a cross-sectional view of a DTI structure inaccordance with some embodiments.

FIG. 5 illustrates a method of forming a DTI structure in accordancewith some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of this disclosure.Specific examples of components and arrangements are described below tosimplify the present disclosure. These are, of course, merely examplesand are not intended to be limiting. For example, the formation of afirst feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Some semiconductor devices utilize deep trench isolation (DTI)structures to isolate neighboring active regions of a semiconductorsubstrate from one another. These DTI structures are formed by using anetch process to form a deep trench within the semiconductor substrate,which is then filled with a fill material. In some applications, afunctional layer is disposed over an upper surface of the semiconductorsubstrate prior to etching the deep trench. The functional layer canenhance the performance of the semiconductor device, but also comprisesone or more potential contaminants for the substrate. In some instances,the etch process used to form the deep trench dissociates thesecontaminants from the functional layer, and the dissociated contaminantsthen diffuse into the semiconductor substrate through sidewalls of thedeep trench as the deep trench is being formed. These contaminants candegrade performance of the final semiconductor device, for example bylessening the isolation provided by the resultant DTI structure or bychanging optical properties near an edge of the DTI structure.

Accordingly, some embodiments of the present disclosure relate toimproved DTI structures, such DTI structure 112A as shown in FIG. 1. Tomitigate contaminants from dissociating from a functional layer 109 intolower DTI sidewall regions 116 b, the DTI structure 112A includes aprotective capping layer 108 and a protective sleeve 122 arranged over asemiconductor substrate 104. During manufacturing, the capping layer 108and protective sleeve 122 work cooperatively to limit dissociation ofthe functional layer 109 while the DTI structure 112A is formed. Inparticular, to form this DTI structure 112A, a first etch process formsa shallow trench which extends to depth 201. Because this first etchprocess etches away a portion of the functional layer 109 when formingthis shallow trench, the first etch process can dissociate contaminantsfrom the functional layer 109 as the functional layer 109 is beingetched away. To limit the extent of any contaminants contaminating adeeper region of the DTI structure near lower DTI sidewalls 116 b, thefirst etch stops shortly after the functional layer 109 has been fullyremoved from the shallow trench. The protective sleeve 122, typically inthe form of a conformal protective liner, is then formed along upper DTIsidewalls 116 a to cover exposed surfaces of the functional layer 109.While the protective sleeve 122 is in place, a second etch process,typically in the form of an anisotropic etch (e.g., unidirectionalvertical etch), then extends the shallow trench from depth 201 to form adeep trench extending to depth 202. During this second etch process, theprotective sleeve 122 remains in place to continuously cover thefunctional layer sidewalls 109 a to prevent dissociation of contaminantsfrom the functional layer 109. Therefore, unlike conventional DTIprocesses, the lower DTI sidewall regions 116 b can be formedsubstantially free of contaminants arising from functional layer 109. Afill material 118, such as a continuous dielectric material or adielectric liner with a tungsten core then fills the deep trench to formthe final DTI structure 112A.

In some embodiments, DTI structure 112 a has a deep trench width 114 ina range between about 0.05 and about 0.2 μm as measured between opposingdeep trench sidewalls 116 a. In some embodiments, the DTI structure 112Ais arranged within a high-aspect-ratio deep trench having a first depth120 greater than about 0.5 microns (μm) as measured from an uppersubstrate surface 104 a. The deep trench can be tapered (i.e., narrows)along a direction 202, such that the width 114 has a maximum value 214Aits top, and a minimum value 214B at its bottom. In some embodiments,the protective sleeve 122 has a sleeve width 168 in a range betweenabout 0.001 μm and about 0.01 μm.

It will be appreciated that the protective sleeve 122 and correspondingmanufacturing techniques, some examples of which are provided furtherbelow, can manifest themselves in a variety of different semiconductordevice technologies. One particular technology where such a protectivesleeve is advantageous is in the area of photovoltaic devices, asdescribed below.

FIG. 2A illustrates a cross-sectional view of a photovoltaic device 200Acomprising first and second pixels 202A, 202B formed within asemiconductor substrate 204 (e.g., silicon, germanium, gallium arsenide,etc.), and separated by DTI structure 212A. The first and second pixels202A, 202B include first and second photodiodes 230A, 230B,respectively, made up of a p-type region 232 formed within an n-typesubstrate region 204, such that a depletion region 238 is formed beneathan upper semiconductor surface 210 about opposite sides of p-n junction240. During operation of photovoltaic device 200A, when incidentradiation 206 of sufficient energy strikes the first or secondphotodiode 230A, 230B, it creates an electron-hole pair (i.e., electron250 and hole 252). The hole 252 is accelerated toward anode 242, and theelectron 250 is accelerated toward cathode 246 to produce aphotocurrent. A color filter layer 264 is optionally disposed over anupper capping surface 234 of first and second pixels 202A, 202B, and amicro-lens 270 is optionally disposed over the color filter layer 264 insome embodiments.

The first and second pixels 202A, 202B include a functional layer 209disposed over an upper semiconductor surface 210 of the semiconductorsubstrate 204, and a capping layer 208, such as an oxide (e.g., SiO₂)disposed over the functional layer 209. In some embodiments, thefunctional layer 209 comprises an antireflective coating, such ashafnium oxide (HfO₂) or an oxide and HfO₂ heterostructure (Ox/HfO₂) forexample, to increase the amount of incident radiation 206 absorbed bythe first and second pixels 202A, 202B.

The first DTI structure 212A comprises a fill material 218 (e.g., oxide,tungsten) disposed within a deep trench. The deep trench has a deeptrench width 214 as measured between opposing deep trench sidewalls 216.The first DTI structure 212A is formed though the capping layer 208 andthe functional layer 209, and extends beneath the upper semiconductorsurface 210 to a first depth 220. A protective sleeve 222 (e.g., siliconoxide (SiO₂), silicon nitride (SiN)) is arranged partially along thesidewalls 216 of the deep trench (or equivalently, the first DTIstructure 212A), between the fill material and 218 the functional layer209. The protective sleeve 222 extends along the sidewalls 216 beneaththe upper semiconductor surface 210 to a second depth 224, which is lessthan the first depth 220.

The protective sleeve 222 is configured to prevent etching of thefunctional layer 209, which prevents contaminants from the functionallayer 209 from diffusing into the first and second pixels 202A, 202Bthrough the sidewalls 216 of the deep trench during formation of thefirst DTI structure 212A, during the deep trench etch. To form theprotective sleeve 222, a first etch process forms a recess within theprotective and functional layers 208, 209, which extends to the seconddepth 224 below the upper semiconductor surface 210. The protectivesleeve 222 is then formed along sidewalls 216 of the recess, and coversexposed surfaces 211 of the functional layer 209. After formation of theprotective sleeve 222, a second etch process then extends the recess toform a deep trench with the first depth 220, while the protective sleeve222 prevents contaminants from the functional layer 209 from penetratingthe first or second pixel 202A, 202B through the sidewalls 216 of thedeep trench.

For the embodiments of FIG. 2A, the protective sleeve 222 is illustratedas extending below the upper semiconductor surface 210 to ensure thatthe exposed surfaces 211 of the functional layer 209 are fully coveredwith some additional overlap margin of the protective sleeve 222 pastthe exposed surfaces 211. In some embodiments, however, the second depth224 can be essentially zero (i.e., no additional overlap margin). Theprotective sleeve 222 has a lower edge that remains spaced apart fromthe bottommost surface of the deep trench. This spacing is presentbecause the lower deep trench portion extending below the protectivesleeve 222 (i.e., the first depth 220 minus the second depth 224) isformed by the second etch process, which occurs after formation of theprotective sleeve 222.

As will be appreciated in more detail further herein (e.g., in thedescription of embodiments of FIGS. 3A-3F), the protective sleeve 222also reduces the deep trench width 214 from an optical opacitystandpoint. Adjacent pixels of the array can experience electricalcrosstalk due to the diffusion of carriers (i.e., electrons or holes),created by the incident radiation 206 from an illuminated pixel to aneighboring pixel. Adjacent pixels can also experience optical crosstalkdue to scattering of the incident radiation 206 from the illuminatedpixel to the neighboring pixel. In order to mitigate against opticalcrosstalk, the fill material 218 is opaque to the incident radiation206, and therefore absorbs or reflects the incident radiation 206.Consequently, the first DTI structure 212A in some regards reduces theamount of surface area on the semiconductor substrate 204 that canabsorb the incident radiation 206. Therefore, in embodiments where theprotective sleeve 222 is optically transparent, the presence of theprotective sleeve 222 can reduce optical opacity over the deep trenchwidth 214 and increases an effective width 226 of the first and secondpixels 202A, 202B. This can increase the amount of incident radiationthat can be absorbed by the photovoltaic device 200A, and consequentlyincreases its quantum efficiency (QE).

FIG. 2B illustrates a cross-sectional view of a photovoltaic device200B, which is similar in many respects to FIG. 2A but which includes adielectric liner 254 configured to trap charge and reduce dark current.Dark current is a condition that can degrade image quality and occurswhen the photovoltaic device produces current even when light is notimpingent on the photodiodes. To mitigate dark current, the dielectricliner 254 is disposed along a lower surface 256 and the sidewalls 216 ofthe deep trench prior to introducing the fill material 118. Thedielectric liner 254 consequently separates the fill material 218 fromthe semiconductor substrate 204. In some embodiments, the dielectricliner 254 comprises HfO₂ and/or oxide (e.g., SiO₂). In some embodiments,the dielectric liner 254 comprises HfO₂ doped with aluminum (Al),tantalum (Ta), cobalt (Co), germanium (Ge), or other appropriate dopant.

FIG. 2C illustrates a cross-sectional view of a photovoltaic device 200Ccomprising first and second photodiodes 230A, 230B that are separated bya third DTI structure 212C. The third DTI structure 212C includes adielectric liner 254 to provide electrical isolation and/or chargetrapping, as well as a tungsten body 218C filling a core region of thedeep trench. In instances where the deep trench is a high-aspect-ratiodeep trench, the deep trench may be problematic to fill with someconventional fill techniques and fill materials such as oxide. As such,the third DTI structure 212C uses tungsten (W) as the fill material218C. Tungsten has an advantage over some conventional fill materialsbecause its good fill-properties ease filling of the high-aspect-ratiotrench, and because it can help prevent electric and optical crosstalkbetween the first and second photodiodes 230A, 230B. When tungsten isused as fill material 218C, a seed layer 266 comprising titanium nitride(TiN) is disposed over the dielectric liner 254 on the lower surface 156and the sidewalls 216 of the deep trench. The seed layer 266 promotestungsten deposition within the high-aspect-ratio deep trench.

Additionally, FIG. 2C shows an example where an anti-reflective layer258, passivation layer 260, and capping layer are each disposed over thesubstrate 204. This configuration can also be used in other embodiments,although it was not illustrated for purposes of conciseness. In someembodiments of FIG. 2C, the anti-reflective layer 258 comprises hafniumoxide (HfO₂), or an oxide and HfO₂ heterostructure (Ox/HfO₂), configuredto prevent reflection of incident radiation. In some embodiments, thepassivation layer 260 comprises silicon nitride (SiN), silicon dioxide(SiO₂), titanium dioxide (TiO₂), or tantalum oxide (Ta₂O₅) configured toreduce electron-hole recombination near the upper semiconductor surface210. The capping layer 262 can comprise an oxide, such as SiO₂, or anitride, such as SiN, for example.

FIGS. 3A-3F illustrates a series of cross-sectional views thatcollectively depict forming the DTI structure 112A. It is appreciatedthat formation of the other DTI structures of FIGS. 2A-2C follows byanalogy. FIG. 3A illustrates a cross-sectional view a photovoltaicdevice 300 comprising a functional layer 109 disposed over an uppersemiconductor surface 110 of a semiconductor substrate 104, and acapping layer 108 disposed over the functional layer 109. In someembodiments, the capping layer 108 comprises an oxide layer (e.g., SiO₂)with an oxide thickness 302 sufficient to withstand a CMP step (e.g.,See FIG. 3F). In some embodiments, the oxide thickness 302 is in a rangeof about 1 μm to about 5 μm. In some embodiments, the functional layer109 comprises HfO₂ configured as an anti-reflective coating. In someembodiments, the functional layer 109 further comprises Ta₂O₅ configuredto passivate the upper semiconductor surface 110.

In FIG. 3B, an upper capping surface of the capping layer 108 is exposedto a first etchant 304 that forms a recess 306 within the capping andfunctional layers 108, 109. This recess 306 extends beneath the uppersemiconductor surface 110 to a second depth 124. In some embodiments,the second depth 124 is zero such that a bottom surface of the recess306 coincides with the upper semiconductor surface 110. In someembodiments, the first etchant 304 comprises a fluorine (F₂) based gasto insure a high-aspect-ratio for the recess 306. Various other wet anddry etchants may be used, including, but not limited to, chlorine (Cl₂)or hydrogen bromide (HBr). After formation of the recess, a protectivelayer 322 is disposed along a lower surface 156 and sidewalls 116 of therecess 306. In some embodiments, the protective layer 322 comprisesoxide (e.g., SiO₂). In some embodiments, the protective layer 322comprises nitride (e.g., SiN). In some embodiments, the protective layer322 comprises a thickness in a range of about 0.001 μm to about 0.01 μm.

In FIG. 3C, the structure is exposed to a second etchant 308 thatfurther extends the recess 306 below the upper semiconductor surface 110to a second depth 120, to form a deep trench 310. The second etchant 308etches away portions of the protective layer 322 disposed along a lowersurface 156 of the recess 306, while leaving portions of the protectivelayer 322 disposed on the sidewalls 116 substantially intact to form aprotective sleeve 122. This protective sleeve 122 protects the sidewalls116 and prevents etching of the functional layer 109 by the secondetchant 308. The protective sleeve 122 also reduces the deep trenchwidth 114 of the recess 306 prior to exposing the semiconductorsubstrate 104 to the second etchant 308, such that the deep trench 310has a deep trench width 114 as measured between inside edges of theprotective sleeve 122.

In some embodiments, the second etchant 308 comprises a fluorine (F₂)based gas to ensure a high-aspect-ratio for the deep trench. It isappreciated that fluorine-based etch chemistries are utilized to achievehigh-aspect-ratio trenches within a silicon (Si) substrate due to theirhigh efficiency free radical disassociation and resulting high etchrates. However, the fluorine based etch is essentially an isotropicprocess. Consequently, the protective layer 322 helps to achieveanisotropy while etching with the second etchant, to maintain ahigh-aspect-ratio deep trench 310.

In FIG. 3D, a dielectric liner 154 is disposed along the upper cappingsurface 134, sidewalls 116, and lower surface 156 of the deep trench310. In some embodiments, the dielectric liner 154 comprises HfO₂configured to act as a charge-trapping layer to minimize dark currentwithin the photovoltaic device 300. In some embodiments, the dielectricliner 154 comprises a thickness in a range of about 0.01 μm to about 0.1μm. In some embodiments, disposal of the dielectric liner 154 comprisesa low temperature oxidation process.

In FIG. 3E, the deep trench 310 is filled with a fill material 118(e.g., oxide, tungsten) to form a boundary between a pair ofphotosensitive pixels 312A, 312B formed within the semiconductorsubstrate 104.

In FIG. 3F, the upper capping surface 134 is subjected to aplanarization process (i.e., a CMP) to remove excess fill material 118,resulting in the DTI structure.

FIG. 4 illustrates a cross-sectional view a photovoltaic device 400comprising a functional layer 109 disposed on an upper semiconductorsurface 110 of a semiconductor substrate 104, and a capping layer 108disposed over the functional layer 109. The functional layer 109 isformed by sequentially disposing an anti-reflective layer 158 (e.g.,HfO₂) over the upper semiconductor surface 110 and disposing apassivation layer 160 (e.g., Ta₂O₅) over the anti-reflective layer 158.The capping layer 108 is formed by disposing an oxide layer 162 (e.g.,SiO₂) over the functional layer 109.

During formation of this device, the first etchant 304 etches the HfO₂and Ta₂O₅ within the functional layer 109 to form contaminants 402comprising tantalum (Ta) or hafnium (Hf), which can diffuse into thesemiconductor substrate 104 through upper sidewalls 116 of the deeptrench during the first etch. Therefore, a wet clean is performed priorto exposing the semiconductor substrate 104 to the second etchant 308 toremove the contaminants 402 from within the upper portion of the recess.The protective sleeve 122 is formed after the wet clean, and preventsfurther etching of the functional layer 109 by the second etchant 308.

After the protective sleeve is formed, a second etch is carried out todeepen the trench. The dielectric liner 154 (e.g., HfO₂) is then formedalong the lower surface 156 and the sidewalls 116 of the deep trench,and a seed layer 166 (e.g., TiN) is disposed over the dielectric liner154. Tungsten is then used to fill the remainder of the deep trench.

FIG. 5 illustrates a method 500 of forming a DTI structure in accordancewith some embodiments.

At 502 a functional layer is formed over an upper semiconductor surfaceof a semiconductor substrate. In some embodiments, the functional layercomprises a Ta2O₅ passivation layer. In some embodiments, the functionallayer comprises an Ox/HfO₂ anti-reflective layer.

At 504 a capping layer is formed over the functional layer. In someembodiments, the capping layer comprises oxide configured to withstand aplanarization step (e.g., a CMP), after formation of the DTI structure.

At 506 the upper semiconductor surface is exposed to a first etchant,which forms a recess within the capping and functional layers thatextends beneath the upper semiconductor surface to a first depth. Invarious embodiments, the first etchant comprises a fluorine (F₂),chlorine (Cl₂), or hydrogen bromide (HBr) based etch chemistry.

At 508 a protective layer is formed along a lower surface and sidewallsof the recess. The protective layer is configured to shield exposedsidewalls of the functional layer during subsequent etch steps. Invarious embodiments, the protective layer comprises oxide (e.g., SiO₂),nitride (e.g., SiN), or a combination thereof. In some embodiments, theprotective layer comprises a thickness in a range of about 0.001 μm toabout 0.01 μm.

At 510 the semiconductor substrate is exposed to a second etchant, whichfurther extends the recess below the upper semiconductor surface to asecond depth to form a deep trench. In various embodiments, the secondetchant comprises a fluorine (F₂) based etch chemistry configured toachieve a high-aspect-ratio etch profile. The second etchant removesportions of the protective layer disposed on a lower surface of therecess, while portions disposed on the sidewalls of the recess remainintact to form a protective sleeve that prevents etching of thefunctional layer. The protective sleeve prevents contaminant egressionfrom the functional layer resulting from exposure to the second etchant,which reduces white pixel (WP) effects. The protective sleeve alsoreduces the recess width prior to exposing the semiconductor substrateto the second etchant, such that the deep trench is narrowed by theprotective sleeve to have a deep trench width as measured between edgesof the protective layer. The reduction in the deep trench widthincreases the amount of incident radiation absorbed by the semiconductorsubstrate, which consequently increases the quantum efficiency (QE) of aphotovoltaic device formed within the semiconductor substrate.

Therefore, some embodiments of the present disclosure relate to a deeptrench isolation (DTI) structure configured to enhance efficiency andperformance of a photovoltaic device. The photovoltaic device comprisesa functional layer disposed over an upper surface of a semiconductorsubstrate, and a pair of pixels formed within the semiconductorsubstrate, which are separated by the DTI structure. The DTI structureis arranged within a deep trench. Sidewalls of the deep trench arepartially covered with a protective sleeve formed along the functionallayer prior to etching the deep trench. The protective sleeve preventsetching of the functional layer while etching the deep trench, whichprevents contaminants from penetrating the pair of pixels. Theprotective sleeve also narrows the width of the DTI structure, whichincreases pixel area and subsequently the efficiency and performance ofthe photovoltaic device.

Some embodiments relate to a deep trench isolation (DTI) structure,comprising a semiconductor substrate having an upper semiconductorsurface. A functional layer is disposed over the upper semiconductorsurface, and a capping layer is disposed over the functional layer. Adeep trench, which has a deep trench width as measured between opposingdeep trench sidewalls, is formed through the capping and functionallayers, and extending beneath the upper semiconductor surface to a firstdepth. A fill material fills the deep trench, and a protective sleevearranged partially along the sidewalls of the deep trench between thefill material and the functional layer.

Other embodiments relate to a photovoltaic device, comprising asemiconductor substrate having an upper semiconductor surface. Afunctional layer is disposed over the upper semiconductor surface, and acapping layer is disposed over the functional layer. A pair of pixelsare formed within the semiconductor substrate, and configured to producea current by absorbing incident radiation. A deep trench, which has adeep trench width as measured between opposing deep trench sidewalls,and is configured to isolate the pair of pixels from one-another, isformed though the capping layer and extending beneath the uppersemiconductor surface to a first depth. A fill material fills the deeptrench, and a protective sleeve arranged partially along the sidewallsof the deep trench between the fill material and the functional layer.

Still other embodiments relate to a method of forming a photovoltaicdevice, comprising forming a functional layer over an uppersemiconductor surface of a semiconductor substrate. The method furthercomprises using a first etchant to form a recess within the functionallayer, wherein the recess has a first depth and exposes a portion of thesemiconductor substrate therethrough. The method further comprisesforming a protective layer along a lower surface and sidewalls of therecess. The method further comprises using a second etchant to extendthe recess below the upper semiconductor surface to a second depth toform a deep trench, while the protective layer disposed on the sidewallsprevents etching of the functional layer.

While method 500 has been described as a series of acts or events, itwill be appreciated that the illustrated ordering of such acts or eventsare not to be interpreted in a limiting sense. For example, some actsmay occur in different orders and/or concurrently with other acts orevents apart from those illustrated and/or described herein. Inaddition, not all illustrated acts may be required to implement one ormore aspects or embodiments of the description herein. Further, one ormore of the acts depicted herein may be carried out in one or moreseparate acts and/or phases.

Further, spatially relative terms, such as “over,” “on,” “beneath,”“below,” “lower,” “above,” “upper” and the like, have been used hereinfor ease of description to describe one element or feature'srelationship to another element(s) or feature(s) as illustrated in thefigures. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A deep trench isolation (DTI) structure,comprising: a semiconductor substrate having an upper semiconductorsurface; a functional layer disposed over the upper semiconductorsurface; a capping layer disposed over the functional layer; a deeptrench, which has a deep trench width as measured between opposing deeptrench sidewalls, formed through the capping and functional layers, andextending beneath the upper semiconductor surface to a first depth; afill material in the deep trench; and a protective sleeve arrangedpartially along the sidewalls of the deep trench between the fillmaterial and the functional layer.
 2. The DTI structure of claim 1,wherein the protective sleeve extends along the sidewalls beneath theupper semiconductor surface to a second depth, which is less than thefirst depth.
 3. The DTI structure of claim 1, wherein the protectivesleeve comprises silicon nitride (SiN) or silicon oxide (SiO₂).
 4. TheDTI structure of claim 1, further comprising a dielectric liner formedon a lower surface and sidewalls of the deep trench, and between thesidewalls and the protective sleeve, to separate the fill material fromthe semiconductor substrate.
 5. The DTI structure of claim 4, whereinthe dielectric liner comprises hafnium oxide (HfO₂).
 6. The DTIstructure of claim 1, wherein the functional layer comprises a hafniumoxide (HfO₂) layer configured as an anti-reflective coating.
 7. The DTIstructure of claim 6, wherein the functional layer comprises a tantalumoxide (Ta₂O₅) layer disposed over the HfO₂ layer, and configured topassivate an upper surface of the HfO₂ layer.
 8. The DTI structure ofclaim 1, wherein the capping layer comprises an oxide layer.
 9. Aphotovoltaic device, comprising: a semiconductor substrate having anupper semiconductor surface; a functional layer disposed over the uppersemiconductor surface; a capping layer disposed over the functionallayer; a pair of pixels formed within the semiconductor substrate, andconfigured to produce a current by absorbing incident radiation; a deeptrench, which has a deep trench width as measured between opposing deeptrench sidewalls, and is configured to isolate the pair of pixels fromone-another, formed though the capping layer and extending beneath theupper semiconductor surface to a first depth; a fill material in thedeep trench; and a protective sleeve arranged partially along thesidewalls of the deep trench between the fill material and thefunctional layer.
 10. The photovoltaic device of claim 9, wherein theprotective sleeve extends along the sidewalls beneath the uppersemiconductor surface to a second depth, which is less than the firstdepth.
 11. The photovoltaic device of claim 9, further comprising adielectric liner disposed on a lower surface and sidewalls of the deeptrench, and between the sidewalls and the protective sleeve, to separatethe fill material from the semiconductor substrate.
 12. The photovoltaicdevice of claim 11, wherein the dielectric liner is configured to trapcharge to reduce dark current within the pair of pixels.
 13. Thephotovoltaic device of claim 9, wherein the functional layer compriseshafnium oxide (HfO₂) configured as an anti-reflective coating.
 14. Thephotovoltaic device of claim 9, wherein the functional layer comprisestantalum oxide (Ta₂O₅) configured to as a passivation layer.
 15. Amethod of forming a photovoltaic device, comprising: forming afunctional layer over an upper semiconductor surface of a semiconductorsubstrate; using a first etchant to form a recess within the functionallayer, wherein the recess has a first depth and exposes a portion of thesemiconductor substrate therethrough; forming a protective layer along alower surface and sidewalls of the recess; and using a second etchant toextend the recess below the upper semiconductor surface to a seconddepth to form a deep trench, while the protective layer disposed on thesidewalls prevents etching of the functional layer.
 16. The method ofclaim 15, wherein the protective layer disposed on the sidewalls reducesa recess width of the recess prior to exposing the semiconductorsubstrate to the second etchant, such that the deep trench has a deeptrench width as measured between edges of the protective layer.
 17. Themethod of claim 15, further comprising filling the deep trench with afill material to form a boundary between a pair of photosensitive pixelsformed within the semiconductor substrate.
 18. The method of claim 17,further comprising disposing a dielectric liner along the lower surfaceand the sidewalls of the deep trench prior to filling the deep trenchwith the fill material, to separate the fill material from thesemiconductor substrate.
 19. The method of claim 15, wherein disposingthe functional layer comprises: disposing an anti-reflective layer overthe upper semiconductor surface of the semiconductor substrate; anddisposing a passivation layer over the anti-reflective layer.
 20. Themethod of claim 19, wherein: the anti-reflective layer comprises hafniumoxide (HfO₂); the passivation layer comprises tantalum oxide (Ta₂O₅);the first etchant etches the anti-reflective layer and the passivationlayer to form contaminants comprising tantalum (Ta) or hafnium (Hf)within the semiconductor substrate; and a wet clean is performed priorto exposing the semiconductor substrate to the second etchant to removethe contaminants from within the recess.